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Getting Transistors off Performance Enhancers

The quest to reduce the size of transistors to 20 nanometers of gate length means turning to a whole new architecture. In the context of the European project SODAMOS1, the Institute of Electronics, Microelectronics and Nanotechnology (IEMN)2 in partnership with the University of Louvain-la-Neuve, STMicroelectronics and the Institute of Electron Technology (IET, Warsaw) has chosen a strategy that favors Schottky contacts on weakly doped silicon over conventional ones.

coupe d'un contact Schottky

© IEMN/ISEN.

Cross-section view of a Schottky contact showing excellent process control in laying down iridium silicide to an exact thickness of 3.2 nm.


Moore's Law3 calls for electronic components to shrink in size by half every 30 months, a prediction which has become a goal for microelectronics industry actors. Since 1997 the International Technology Roadmap for Semiconductors (ItrS) has defined its objectives for transistor miniaturisation in just these terms. According to the 2003 edition of this document, the metallic Schottky source/drain approach has been recently recognized as the booster that could extend the lifetime of CMOS technology beyond the ultimate 22 nm node.

The goal of the project SODAMOS, coordinated by the IEMN, is to break down the technological barriers that keep gate manufacture from reaching the goal of 20 nm, particularly for access resistances of contacts. Emmanuel Dubois, researcher at the IEMN and project coordinator, explains that “when the size of a transistor is reduced, the thickness of all the layers must be reduced also in order to preserve correct electrical operation, while the level of doping has to be increased. This forces us to change the architecture completely”.

A MOS transistor4 is composed of three terminals. The first two, the source and the drain, are laid on a silicon substrate and are separated by the third, a metallic gate insulated from the conduction channel by a thin film of silicon dioxide. When the gate receives an electrical charge – a few hundred millivolts is ample – an electric field is created which allows electrons to circulate from the source to the drain by way of the channel.

In conventional technology, the silicon substrate of an n-type transistor is doped with 'donors' impurities in the source and drain regions and with electron acceptors in the channel under the gate. This difference between the two doped regions generates a potential barrier that impedes the flow of electrons between source and drain whenever the gate voltage is below a certain threshold.

When it comes to shrinking a transistor and hence reducing its thickness, doping poses a problem because the thickness of the doped layer is hard to control. Impurities, which are often introduced by ion implantation, spread across the surface in accelerated fashion during thermal activation.

The solution to this limitation is to do without doping. To get their transistors “unhooked,” Emmanuel Dubois and his research team replaced conventional contacts found on doped silicon by a metallic junction on non-doped silicon, a mixture of metal and silicon known as a silicide. These new contacts must in any case present a resistance at least as weak as that of conventional technology. IEMN researchers have managed to reduce the only potential barrier that exists between source and drain, the intrinsic contact resistance known as the Schottky barrier. They accomplish this by using either platinum or erbium silicide, which makes it possible to lower this barrier to less than 0.1 electron-volt.

sodamos_bottom

© IEMN/ISEN.

TEM cross-section of a p-type Schottky-Barrier MOSFET on a 10 nm thick SOI channel with PtSi source/drain, a 200 nm long intrinsic gate, a 2.2 nm thick gate oxide, a 40 nm tungsten gate encapsulated by 20 nm wide nitride spacers and a top oxide layer.


At the end of the project, device integration of p-type MOSFETs with a metallic midgap gate has been demonstrated for the first time. An excellent current drive of 425 µA/µm  coupled to an off-state current of 368 nA is obtained for a gate length of 40 nm. The measured transconductance is 362 mS/mm. This performance is the best ever recorded for a p-type Schottky MOSFET. A comparison to best published Ion/Ioff performance of Schottky MOSFETs indicates that SODAMOS is ranking first with Spinnaker Semiconductor5. Another comparison with conventional MOS technologies developed in major industrial labs shows that SB-MOSFETs steadily progress in terms of current drive capabilities and offer the promise of very high frequency operation. Remarkably, this level of performance is obtained through a drastically simplified and cost-effective manufacturing process.


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Contact

Emmanuel Dubois
Institut d'électronique, de microélectronique et de nanotechnologie (IEMN)
E-mail: emmanuel.dubois@isen.iemn.univ-lille1.fr

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iemn.univ-lille1

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